Internship - Synthesis & Timing/Area RTL Design Analysis (f/m/div)

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Your role Key responsibilities in your new role RTL Design Exploration: Synthesize multiple RTL design variants using a commercial synthesis tool Automation Framework: Utilize an in-house automation framework Timing and Area Analysis: Extract key timing metrics (e.g., WNS, critical path delay, cell/component delays) and area from synthesis reports Data Analysis and Interpretation: Investigate correlations between timing metrics and area

Your profile Qualifications and skills to help you succeed Education/Study Field: Currently studying for a BSc or MSc in Electrical Engineering, Computer Engineering, Computer Science, or similar Skills: Good knowledge of RTL digital design and Verilog/SystemVerilog Interests: Interest in processor architecture and logic synthesis Language Skills: Fluent English skills, both written and spoken

Please attach the following documents to your application

CV in English Certificate of enrollment at university Excerpt of the study regulations for the mandatory internship (if applicable) Latest grades transcript (not older than 6 months) High school report

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Britta Johansson