Working Student - R&D Digital Memory Subsystem (f/m/div)

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Your role Key responsibilities in your new role Focus on the future: Understand and enhanced memory sub system automation environment with EDA tools Take responsibility: Integrate MBIST generation into the subsystem build (wrappers, controllers, constraints, sanity checks) Reliable work: Execute synthesis across diverse configurations; standardize and store KPIs (area, Fmax/slack, power if available, EDA runtime/peak memory, MBIST overhead) Keep up to date: Provide support in RTL design for memory sub system IPs Build robust parsers and data schemas; track provenance (tool versions, seeds, constraints Identify needs: Work with the existing structured results database to surface build and evaluation data Train ML models to identify Pareto‑optimal configurations and recommend next experiments

Your profile Qualifications and skills to help you succeed Study field: A Bachelor's degree in Electrical Engineering, Information Technology or similar studies with focus on electronics Knowledge: Knowledge of VHDL, System Verilog including experience on CPU and memory designs together with functional and corner case verification

Skills

Python for automation/data (pandas/numpy), Bash/Tcl; Git, Linux/Unix RTL/VHDL/System Verilog and timing/SDC basics Logic synthesis/reporting; handling netlists/Liberty Basic knowledge of directed verification Nice to have: MBIST/DFT fundamentals Familiarity with Linux/Unix environments and shell scripting Way of working: Analytical, organized, and curious person. Methodical debugging, proactive and collaborative colleague Language skills: Fluent in English.

Please attach the following documents to your application

• CV in English
• Certificate of enrollment at univ