Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Technology
Irvine, California, United StatesPosted Sep 10, 2026

About the role

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact AI at hyperscale is an architecture problem. Training a frontier model across hundreds of thousands of XPUs, routing over 100 terabits of traffic through a single switch fabric at ~400 nanoseconds of latency, processing optical signals at 1.6T across a data center floor — none of it works without the systems architects, DSP engineers, and algorithm designers who define how data moves, how signals are processed, and how compute is organized at every layer of the stack. At Marvell, that work happens across the full AI interconnect hierarchy: scale-up networks connecting XPUs within a rack using PCIe, UAL, and NVLink-compatible switching; scale-out fabrics interconnecting thousands of XPUs across rows and data center floors through the Teralynx Ethernet switch family — purpose-built for AI, now at 102.4 Tbps with ~400ns latency on the T100; and scale-across connectivity linking geographically distributed data centers through coherent DSP and DCI platforms. The architecture decisions made here define what AI infrastructure can do, at what speed, and at what cost.

The work spans multiple disciplines and multiple markets. On the switching side, teams are architecting the next generation of Teralynx switch silicon — designing forwarding pipelines, congestion control algorithms, traffic management systems, and telemetry architectures for AI fabrics running Ultra Ethernet Consortium protocols at 800G a

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