Analog Design Intern, MS - Summer 2027

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering Test Chip Development team provides hardware validation for custom SRAM, logic, I/O, and security circuits across Marvell business units in advanced semiconductor technology nodes. The team designs and develops test chips, establishes laboratory infrastructures for silicon characterization and measurement collection, and partners with custom circuit design teams to conduct detailed circuit analysis that verifies silicon performance and functionality. What You Can Expect

• Design and verify test chip experiments using Verilog simulation.
• Develop, generate, simulate, and debug Verilog-based test patterns for hardware validation of test chip experiments.
• Develop and maintain laboratory environments that support hardware debug, diagnostics, characterization, and measurement data collection.
• Create software tools and automation scripts (Perl, Python, and Tcl) for design support, hardware characterization, laboratory measurements, data processing, and results analysis.
• Analyze, summarize, document, and present characterization and validation results to engineering teams and stakeholders.

What We're Looking For Currently enrolled in a Master’s Degree in MSEE, MSCE, or a related field with an expected graduation date of Fall 2027 – Summer 2028. Strong understanding of digital logic circuits, memory architectures, I/O circuits, and semiconductor device physics. Proven exp