Internship - Analog Mixed-Signal Design Verification Engineer

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Your role Key responsibilities in your new role Verification Planning: Develop verification plans per device specifications and requirements to ensure coverage of analog and mixed-signal design intent Behavioral Modeling: Generate and maintain Verilog-AMS, SystemVerilog, and mixed-signal behavioral models to support simulation and verification workflows Testbench Development: Develop testbenches, simulation environments, and regression flows for mixed-signal verification Simulation Execution: Create and execute mixed-signal simulation flows to validate device-level and system-level behavior across operating conditions Corner Analysis: Evaluate behavior under nominal and corner conditions to ensure design robustness and performance compliance

Your profile Qualifications and skills to help you succeed

Education: Junior level or higher, actively pursuing a Bachelor’s or Master’s degree in Electrical Engineering or a related engineering field Analog Coursework: Coursework in analog circuits, electronics, signal analysis, or mixed-signal fundamentals strongly preferred Coding Ability: Demonstrated coding or scripting experience in Python, MATLAB, Tcl, or similar tools preferred Languages: Experience with Verilog-AMS and SystemVerilog and familiarity with mixed-signal modeling approaches Cadence Tools: Exposure to Cadence Virtuoso, Spectre, ADE Explorer/Assembler, vManager, and Xcelium preferred Soft Skills: Strong analytical, organizational, and communication skills with ability to collaborate across design and verification teams US citizen or green card holder: This position requires access to documentation that is controlled by the export laws of the United States. Candidates