Internship - Analog Mixed Signal Design

#WeAreIn to create tiny chips and big careers. Are you ready to take the first step of your career? Let's shape the future together! Whether you join as a student, intern or trainee, you'll be part of something real - real projects, real impact, and real opportunities to grow. Are you in?

Your role Key responsibilities in your new role

Design Support: Assist with analog and digital design and verification of mixed-signal IP using the Cadence suite of tools across various SoC scenarios Testbench Development: Create mixed-signal testbenches and execute simulations for digital multiphase buck controllers, integrated power stages, and voltage regulator designs Functional Verification: Perform functional verification of power management circuits including digital multiphase buck controllers and integrated power stages Silicon Evaluation: Conduct bench-level silicon evaluation to characterize IC performance, document results, and prepare structured validation reports Constrained Random Verification: Develop scalable and reusable constrained random testbenches using SystemVerilog and UVM object-oriented methodologies Cross-Functional Collaboration: Partner with analog and digital IC design experts and cross-functional teams to improve unit architecture performance and next-generation IP development Skill Development: Build analog and mixed-signal design competencies by actively contributing to next-generation IP and exploring best-in-class product design solutions

Your profile Qualifications and skills to help you succeed

Education: Currently enrolled in or recently graduated from a Bachelor's or Master's program in Electrical Engineering or a closely related field Cadence Proficiency: Hands-on experience with Cadence tools for schematic creation, netlist generation, and simulation execution in analog or mixed-signal environments Verification Languages: Familiarity with hardware verification languages including SystemVerilog and UVM for constrained random testbench de